`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:08:23 07/05/2015 
// Design Name: 
// Module Name:    tb_soc 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module tb_soc(clk_100M,eoc,sdo,sclk,sdi,csb,convstb,sout,dout); 
  input clk_100M,eoc,sdo;
  output sclk,sdi,csb,convstb;
  output [3:0] sout;
  output [6:0] dout;

  wire clk_50M;
  wire clk_190;
  wire dclk;
  wire avclk;
  wire aclk;
  wire [13:0] vt_ave;
  wire [11:0] soc_bcd;
  wire [13:0] vt_adc;
  wire [9:0] ocv;
  
  clk_half uc1(.clk_in(clk_100M),.clk_out(clk_50M));
  clk_5M uc2(.clk_in(clk_50M),.clk_out(dclk));
  clk_190 uc3(.clk_100M(clk_100M),.clk_190(clk_190));
  
  adc_drive ua1(.dclk(dclk),.eoc(eoc),.sdo(sdo),
  .sclk(sclk),.sdi(sdi),.csb(csb),.convstb(convstb),.vt_adc(vt_adc),.avclk(avclk));
  average ua2(.avclk(avclk),.vt_adc(vt_adc),.vt_ave(vt_ave),.aclk(aclk));
  algorithm ua3(.aclk(aclk),.vt_ave(vt_ave),.ocv(ocv));
  lut ul1(.clka(avclk),.addra(ocv),.douta(soc_bcd));
  led_drive ul2(.clk(clk_190),.soc_bcd(soc_bcd),.sout(sout),.dout(dout));

endmodule
